National Nanotechnology Infrastructure Network

National Nanotechnology Infrastructure Network

Serving Nanoscale Science, Engineering & Technology

Semiconductor Process Development and Integration with SEMulator3D

Presenters:
Dr. David M. Fried, Chief Technology Officer (CTO), Coventor.

Abstract:

Fabrication technologies for leading-edge semiconductor devices are increasingly diverse with logic, S/DRAM and flash memory each manufactured using their own dedicated process technologies. With the critical dimensions of these devices continuing to shrink, process engineers must invent new methods to maintain transistor performance and scaling advancements. This rapid evolution in process technology has led to process flows that require hundreds of steps to fabricate transistors with increasingly sophisticated 3D geometry. Greater process complexity has, in turn, dramatically increased the development effort and cost of bringing new technology nodes to production.

SEMulator3D offers an intuitive, graphical software environment for investigating complex sequences of process steps. With the ability to visualize a process step-by-step in three dimensions, engineers can quickly gain valuable insight into the process and predict problems before fabricating actual devices. SEMulator3D can model hundreds of transistors in only a few minutes on a laptop or workstation.

Bio:

Dr. David M. Fried, is Chief Technology Officer (CTO) Semiconductor of Coventor, where he is responsible for the company’s strategic direction and implementation of its SEMulator3D virtual fabrication 3D process modeling solution. He leads the execution of technology strategy for technology platforms, partnerships, and external relationships. His expertise touches upon such areas as Silicon-on-Insulator (SOI), FinFETs, memory scaling, strained silicon, and process variability. Fried is a well-respected technologist in the semiconductor industry, with 45 patents to his credit and a notable 14-year career with IBM, where he was involved in successive process generations from 65-nanometer and lower. His most recent position was 22nm Chief Technologist for IBM’s Systems and Technology Group. He has Masters and Doctoral Degrees in Electrical Engineering from Cornell University.

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University of Michigan