National Nanotechnology Infrastructure Network

National Nanotechnology Infrastructure Network

Serving Nanoscale Science, Engineering & Technology

Vince Genova

(607) 254-4907

Profile at CNF

Cornell University

Resume

Process Engineer

Vince Genova has been a Process Engineer at CNF since 1999. He spends full time developing and characterizing RIE and ALD processes, particularly as related to MEMS devices. Prior to coming to CNF, we worked at both IBM Yorktown Heights (on GaAs devices) and at Kodak.

Please see Vince's postings on ALD and RIE in the NNIN Process Blog:

Publications:

  • Influence of master fabrication techniques on the characteristics of embossed microfluidic channels, M.Esch, S.Kapur, G. Irizarry, and V. Genova; Lab Chip, 2003, 3, 121-127.
  • Assessing Deep Reactive Ion Etch (DRIE) at CNF, V. Genova and D. Lishan; Oerlikon CHIP 3/2008.
  • Characterization and comparison of fused silica etch processes in fluorocarbon based ICP chemistries, C.C.Welch and V.J.Genova; PESM 2010-Grenoble, France
  • Band alignment of atomic layer deposited HfO2 on clean and N passivated germanium surfaces, A.Rumaiz, J.Woicik, G. Carini, D.Siddons, E.Cockayne, E.Huey, P.Lysaght, D.Fischer, and V.Genova; Applied Physics Letters 97, 242108 (2010).
  • Experimental and theoretical studies on MEMS piezoelectric vibrational energy harvesters with mass loading, R.Andosca, T.G.McDonald, S.Rosenberg, V.Genova, J.Keating, C.Benedixen, and J.Wu; Sensors and Actuators A vol.178, May 2012, p.76-87.
  • Lithographically Fabricated Gratings for the Interferometric Measurement of Material Shear Moduli Under Extreme Conditions, A.Gleason, R.Tiberio, W.Mao, S.Ali, C.Bolme, A.Lazicki, V.Genova, G.Bordonaro, J.Treichler, and J.Eggert; JVSTB 2013.
  • Formation of Nanoscale Structures by Inductively Coupled Plasma Etching, C.C.Welch, D.Olynick, Z.Liu, A.Holmberg, C.Peroz, A.Robinson, M.Henry, V.Genova, and D.Ng; SPIE proceedings of ICMNE 2012 Russia.
  • Dielectric Etching at the Nanoscale, V.J.Genova, Nanoscale Plasma Processing Seminar, Microsystems Technology Laboratories (MLT) at MIT-December 2012.