UT-QUANT at NNIN
CV Simulator for Silicon MOS Structures
The UT-QUANT provides quasi-static CV characteristics for one-dimensional silicon MOS structures. It has the ability to determine quantization effects within MOS inversion layers. The leakage current due to electron tunneling through thin gate oxides in MOS devices can also be calculated. The code self-consistently calculates the sheet carrier concentration in the device for a range of biases and from this builds up the CV characteristics. Options are available to perform both semi-classical and quantum calculations to gauge the differences predicted by the two models. In larger systems, semiclassical approaches are computationally more efficient and provide a reasonable degree of accuracy. For smaller MOS systems, care must be taken to address quantization issues related to nanoscale dimensions. The code also has the ability to incorporate strain effects into device characteristics.
- CV characteristics of silicon MOS devices
- Leakage current due to electron tunneling through oxide layers
- Inversion and accumulation layer band diagrams and wave functions
W.-K. Shih, S. Jallepalli, G. Chindalore, C. Maziar, A. F. Tasch (University of Texas, Austin)
- Some pointers on installing UTQUANT: (install instructions)
- Users Guide (pdf)
- Getting a copy of UTQUANT or running it on the CNF cluster: Contact Derek Stewart, stewart (at) cnf.cornell.edu
Relevant Research Articles:
- Jallepalli, S., Bude, J., Shih, W.-K., Pinto, M. R., Maziar, C. M., and Tasch, A. F., "Electron and hole quantization and their impact on deep submicron p- and n- MOSFET characteristics", IEEE Transactions on Electron Devices, 44, 297, (1997).
- Chindalore, G., Hareland, S. A., Jallepalli, S., Tasch, A. F., Maziar, C. M., Chia, V. K. F., and Smith, S., "Experimental determination of threshold voltage shifts due to quantum machanical effects in MOS electron and hole inversion layers", IEEE Electron Device Letters, 18, 206, (1997).
- Mudanai, S., Fan, Y., Quyang, Q., Tasch, A. F., Banerjee, S. K., "Modeling of Direct Tunneling Current Through Gate Dielectric Stacks", IEEE Transactions on Electron Devices, 47, 1851, (2000).
- Fan, Y., Nieh, R. E., Lee, J. C., Lucovsky, G., Brown, G. A., Register, L. F., Banerjee, S. K., "Voltage and Temperature Dependent Gate Capacitance and Current Model: Application to ZrO2 n-channel MOS Capacitor", IEEE Transactions on Electron Devices, 49, 1969, (2002).
stewart (at) cnf.cornell.edu
Cornell Nanoscale Science and Technology Facility