Deep Silicon Etching at Stanford-Plasma Therm Versaline DSE
Justin Snapp, Stanford Nanofabrication Facility
For microelectromechanical systems (MEMS) and other applications, deep reactive ion etching (DRIE) of silicon is an important process enabling deep etching and high aspect ratio structures. To achieve high aspect ratio structures and high selectivity to the masking material, DRIE utilizes a process of time division multiplexing (TDM) involving rapid cycles of deposition and etch steps.
The VERSALINE™ Deep Silicon Etch (DSE®) system incorporates several innovative and enabling technologies. The system uses ALD style gas switching to rapidly alternate between the continuously flowing process gasses, enabling sub-second switching time. This rapid switching time allows for a reduction in the sidewall scalloping inherent in the DRIE process. To address the challenge of maintaining a stable plasma during these rapid cycles, a solid-state frequency tuning network is used instead of a traditional mechanically tuned matching network. The system software also allows for multiple deposition and etch steps to be defined within each loop of the TDM process. This offers and extra degree of freedom for optimizing etch rate, surface roughness, and sidewall profile. To control the sidewall profile of deep trenches and counteract aspect ratio dependent etch (ARDE) effects, process parameters, such as time, power and pressure, can be swept using a power-law function.
Process Recipe Run Details
|Parameter Name||Unit||Dep||Etch A||Etch B|
|RF Forward Power||V||10 (15%)||250(20%)||10 (15%(|
|ICP Forward Power||W||2000||3000||3000|
|Number of loops =100 (750 seconds)|