DRIE on Si and Dielectrics at Michigan Lurie Nanofabrication Facility
Kevin Owen , University of Michigan
Posted January 2013
With the recent expansion at the LNF, three new SPTS ICP systems were installed: two Pegasus deep silicon etchers and one APS system, designed for deep glass and dielectric etching. These tools have pushed the limits of high aspect ratio plasma etching. The first part of this paper covers deep silicon etching using the SPTS Pegasus tool, including standard process capabilities as well as two novel processes developed by users at the LNF. The second part of the paper discusses recent advances made on the SPTS APS system for etching fused silica.
Part I: Deep Silicon Etching
The SPTS Pegasus tools at the LNF are designed for Bosch process etching of silicon, using SF6 as the etch gas and C4F8 as the passivating gas. The tools are designed for high gas flow (several hundred sccm) and high ICP power (up to several thousand watts) in order to create a high density of reactive species to increase etch rate. They are also designed for very fast switching between the etch and passivation step, which can assist in tuning a recipe to have less scalloping and undercut, which is critical for creating a smooth, vertical etch. Lastly, the Pegasus tools are equipped with a low frequency, pulsed bias, which prevents charge buildup and thus reduces undercut and notching at dielectric interfaces.
The standard processes that are run in the Pegasus tools have etch rates ranging from several microns per minute to over 12 microns per minute. A recipe could be tuned to have a much higher etch rate, but they are more difficult to control, particularly because of the heat generated. Scalloping and undercut are two of the most well documented concerns with Bosch process etching, because they lead to rough sidewalls which are not always ideal. For faster etch rates, this scalloping is on the order of 2um in pitch, with around 1um of undercut. This is because a faster etch rate requires a longer etch step time, and the etch step is inherently isotropic. For processes that require a smoother sidewall, there is a slower recipe that has a scallop pitch of only a couple hundred nanometers and less 100nm of undercut.
At the LNF, several users have developed and characterized advanced processes for DRIE, particularly for high aspect ratio, sub-micron features. Mukherjee, et al. developed a process for etching a 200nm pitch grating pattern with 100nm openings to 6µm deep . This recipe takes advantage of the tools’ fast switching and precise parameter control to reduce scalloping and undercut to less than 10nm and create a very vertical etch (Figure 1).
This recipe is very well tuned for submicron features. However, for features much larger than a couple microns, the recipe is no longer stable and will generally result in grassing. Depending on the range of features desired, recipe tuning may be required, particularly when pushing tool limits. Another recipe developed at the LNF is optimized for extremely high aspect ratio (80-100:1) features sized between 1 and 10µm . This recipe uses the tools’ ability to ramp individual parameters over the course of the etch to reduce narrowing and etch stop in deep features. In high aspect ratio etching, the parameters used at the beginning of a process will not be effective at etching later in the process, due to the reduced ion bombardment and gas transport in deep trenches. Thus, by ramping parameters such as bias power, pressure, and switching time, the process will gradually shift throughout the etch and maintain etch rate and sidewall profile. An SEM of trenches etched by this process is shown in Figure 2.
|Figure 1: 200nm pitch grating etched to 6µm in the SPTS Pegasus (P. Mukherjee, et al. ).||Figure 2: 1 to 5 µm trenches etched for two hours in the SPTS Pegasus. With 2.5 hours, the 5 µm trench would be 400 µm deep (K. Owen )..|
Part II: Deep Fused Silica Etching
Recently, the LNF developed an advanced process for deep etching of fused silica and quartz, aimed at through wafer etching of these substrates. Etching dielectric materials such as silicon dioxide is significantly more difficult than silicon etching, mainly due to the physical nature of the etch. Silicon readily etches in a fluorine-based plasma with little or no bias – only fluorine radicals are needed to react with the silicon. Silica, however, requires a high activation energy to break the Si-O bonds. The high bias power necessary to impart this energy on the ions bombarding the wafer is detrimental to selectivity – most materials, including standard photoresist are easily sputtered away by these high energy species. Additionally, the etch gas is typically a fluorocarbon species, which will also passivate the surface of the sample and the chamber itself during the etch. Too much of this passivating gas can even cause etch stop.
The recipe developed at the LNF uses C4F8 as the reactive species, heavily diluted in helium. The dilution reduces the amount of reactive species that can passivate the sample and chamber. This process is designed to use KMPR or SU-8 as an etch mask. These are significantly easier to pattern than thick silicon or nickel, which are the most commonly used etch masks, due to their high selectivity. Unlike standard photoresists, these resists are tolerant to very high temperatures and plasma energies and can be patterned in very thick layers, providing a strong, thick mask. The process also flows a small amount of hydrogen, which greatly increases the mask selectivity by hardening the resist and also limiting the fluorine radicals, which are highly reactive with many photoresists.
This process has achieved depths of 50µm for large (greater than 20µm) features, limited by the thickness of the mask used. Mask selectivity is typically 5:1 for a KMPR mask. Figure 3 shows a cross section of trenches etched using this process. A paper will be presented at MEMS 2013 covering further advances of this process.
|Figure 3: Deep fused silica etch using APS system. From left to right: bulk etch, 10 µm, 8 µm, 6 µm.|
 P. Mukherjee, et al. J. Vac. Sci. Technol. B. 28, 6 (2010).
 K. Owen, et al., MEMS, 2012 IEEE 25th Intl. Conf., 251-254 (2012).