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Nanoscale Etching of Silicon with High Mask Selectivity using SF6/C4F8/Ar ICP Etching in Plasma-Therm SLR 790 System

Yung-Jr Hung (NTUST, Taiwan) and Brian Thibeault (UCSB)

September 2013

Nanoscale and fine-scale etching recipes of silicon are needed more and more for silicon-based photonics and other applications at the UCSB facility. This particular work, done a few years ago, highlights the recipes developed in the UCSB nanofabrication facility for these applications. The original application pursued by this work was for silicon-based photonic crystal formation.

The resist patterns were produced by Laser Interference Lithography (LIL) using an exposure system containing a beam expanded HeCd laser and home-built Lloyd-Mirror stage. OHKA THMR M100 resist on top of Brewer Science XHRiC-11 ARC (Anti-Reflection Coating), followed by Oxygen RIE was used to produce 2-D structures on top of silicon for the etching development. Figure 1 below shows a typical resist profile, prior to ARC oxygen etching.

 

 

 

 

 

 

 

 

 

 

 

 

 

Figure 1: Resist profile for nanoscale dot array formed by LIL.

After ARC etching in oxygen RIE, the silicon is etched in a Plasma-Therm SLR 790 ICP etching system using SF6, C4F8, and Ar. The SF6/Ar serves as the etching component and the C4F8 provides sidewall passivation, just as in the Bosch process. Pressure is kept at 19mT, ICP power at 850W, and Sample RIE Bias at 9W for the gas variation study. Table 1 summarizes our etch results and figure 2 shows the etch profiles of final patterns after resist removal. Etch times were adjusted after initial characterization to produce roughly equal etch depths for all samples. Slight changes to the gas chemistry (flows of SF6 and C4F8) result in sharp changes in the balance of fluoro-polymer formation and deposition versus silicon etching, resulting in reduced etch rates and increased outward tapers as C4F8 is increased and SF6 is decreased. Resist/ARC etch selectivity as high as 85:1 and a slight lateral etch rate of about 5nm/min, was measured for recipe B.

Table 1 Profiles of resultant patterns under different DRIE process conditions
 
DRIE Process Conditions
Resultant Profiles
Samples in figure 2
Time
(min)
C4F8
(sccm)
SF6
(sccm)
Ar
(sccm)
Height
(um)
Slope of profile
(nm/um)
Sample A and D
3
50
30
20
1.2
-41.9
Sample B and E
5
52
28
20
1.11
+7.2
Sample C and F
14
54
26
20
1.22
+10..3

 

Figure 2

For more complete details, please see the published paper in IEEE Journal of Selected Topics in Quantum Electronics 17(4) (2011) p. 869-77

Tags: 
UCSB
Silicon
ICP
RIE

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